Intel IP Logic Design Engineer in Folsom, California

Job Description

In this position, you will be a member of an Intel ITG-CIG Security COE IP Design team based in Folsom working on leading edge IP designs. The team is looking for engineers with:

  • Strong RTL Design and Validation experience

  • Proven track record of successful first time delivery of projects

  • Self-starter with the ability to assume leadership roles

  • Ability to work well in a diverse team environment

  • Excellent communication, interpersonal, and problem solving skills,

  • Motivated, self-directed, and able to work effectively both independently and in a team

  • Good planning skills

Your responsibilities will include but not be limited to:

  • Developing the micro-architectural specification of complex design blocks

  • Responsible for the logic implementation of complex design blocks using RTL coding techniques

  • Working with pre-Silicon validation engineers to develop cluster level directed/random tests and environments

  • Provides IP integration support to SoC customers and represents RTL team.

  • Performs Logic design for design blocks of Soft IP SIP

  • Participates in the development of Architecture and Micro-architecture specifications for the Logic blocks

  • Provides IP integration support to SoC customers and represent SIP team


Minimum Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering or a related discipline with 4+ years’ experience in IP and SoC design or a Master's degree in Electrical Engineering, Computer Engineering or a related discipline with 3+ years’ experience in IP and SoC design

Preferred Qualifications

  • 7+ years of industry experience in IP and SoC design

  • Strong experience/background in RTL level Digital IC Design using System Verilog and/or Verilog

  • Experience with languages and standards such as Verilog, System Verilog, Perl, Shell scripting, UPF, OCP, PCIe, IOSF, UPF2.0

  • Experience in unit level validation environment development, test plan generation and test case implementation for the verification of design blocks

  • Experience with industry standard design development tools and methodologies

  • Experience with logic simulation tools such as VCS

  • Working knowledge of Synthesis and Static Timing Analysis STA with Design Compiler and Primetime

  • Working knowledge of Conformal, CDC, Spyglass-LP, Spyglass-DFT, Caliber and other frontend/backend design quality check tools

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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